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Knowledge Institute of Technology , Salem , India
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Karpagam Institute of Technology , Coimbatore , India
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Karpagam Institute of Technology , Coimbatore , India
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Karpagam Institute of Technology , Coimbatore , India
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Karpagam Institute of Technology , Coimbatore , India
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Karpagam Institute of Technology , Coimbatore , India
Karpagam Institute of Technology , Coimbatore , India
This paper describes the design of the Carry Look-ahead Adder (CLA), which uses the Inexact Speculative Adder (ISA). The speculative adder is designed for high-speed VLSI architecture and features advanced compensation techniques and optimized hardware efficiency. Considered to be the adder's critical path, it is finely pipelined to contain a few logic gates along its carry propagation chain. This increases the frequency of operation by employing CLA, which is pipelined with some logic gates. To lower the model's power consumption, a separate planned ISA stage has been clocked gated. The Field Programmable Gate Array (FPGA) framework is used for hardware implementation and punctuality verification. The carry look-ahead adder operates at the clock frequency of 324 MHz. A power and area study of a 32-bit planned ISA is performed using CMOS technology. Our device's power consumption and chip area consumption are lower than those of a conventional speculative adder, at 2 mm and 9.68 mW, respectively.
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